The present invention relates to a solid state image sensor and a method for manufacturing the same, and, more particularly, to a charge-coupled device (CCD) solid state image sensor and a method for manufacturing the same.
FIG. 1 is a schematic diagram of a known solid state image sensor 100 of a frame transfer method.
The CCD solid state image sensor 100 includes an image sensing section 100i, a storage section 100s, a horizontal transfer section 100h and an output section 100d. The image sensing section 100i includes a plurality of parallel shift registers, which are arranged in the vertical direction. Each bit of each register forms a light receiving pixel. The storage section 100s includes a plurality of optically shielded shift registers that are arranged in series with the shift registers of the image sensing section 100i. Each bit of each optically shielded shift register forms a storage pixel. The horizontal transfer section 100h includes a single shift register arranged in the horizontal direction. The output of each shift register of the storage section 100s is supplied to each bit of the single shift register. The output section 100d includes a capacitor, which temporarily stores charges transferred from the horizontal transfer section 100h, and a reset transistor, which discharges the charges stored in the capacitor.
After information charges stored in each light receiving pixel of the image sensing section 100i have been transferred to the storage pixels of the storage section 100s, the information charges are transferred from the storage section 100s to the horizontal transfer section 100h, line by line. Then, the information charges are transferred from the horizontal transfer section 100h to the output section 100d, pixel by pixel. The output section 100d converts the information charges to a voltage signal, pixel by pixel, and supplies the voltage signal to an external circuit as a CCD output signal.
FIG. 2 is a schematic plan view of the image sensing section 100i. FIG. 3 is a schematic sectional view of the image sensing section 100i taken along line 3xe2x80x943 of FIG. 2. FIG. 4 is a schematic sectional view of the image sensing section 100i taken along line 4xe2x80x944 line of FIG. 2.
A P-type diffused layer 2, which is also called a device formation region, is arranged on the surface of an N-type silicon substrate 1. Parallel high-concentration P-type isolation regions (channel stops) 3 are arranged on the surface of the diffused layer 2 in the vertical direction of FIG. 2. N-type diffused layers 4 are arranged on the surface of the diffused layer 2 between the isolation regions 3. A channel region, which is the transfer route of information charges, is formed in each of the diffusion regions 4. A plurality of parallel transfer electrodes 6, which comprise a polycrystaline silicon, are arranged on the diffusion regions 4 at predetermined intervals via an insulating film 5, which comprises a silicon oxide film. For example, 3-phase transfer clocks xcfx861 to xcfx863 are applied to the transfer electrodes 6, and the potential of the channel region is controlled.
FIG. 5 is a diagram showing a profile of the potential in the depth direction of the silicon substrate 1 along line 5xe2x80x945 of FIG. 3.
The potential level on the surface of the silicon substrate 1 is determined by the potential applied to the transfer electrodes 6, and the potential levels at deeper locations within depth of the silicon substrate 1 are determined by the potential applied to the silicon substrate 1. When charges are stored, the potential is gradually lowered from the gate insulating film 5 toward the middle of the N-type diffused layers 4 and shows a minimum value in the middle of the N-type diffused layers 4. The potential gradually increases from the middle of the N-type diffused layers 4 toward the middle of the P-type diffused layer 2 and shows a maximum value in the middle of the P-type diffused layer 2. Subsequently, the potential decreases toward the middle of the N-type silicon substrate 1. A potential barrier is formed according to the difference between the minimum value of the potential in the N-type diffused layers 4 and the maximum value of the potential in the P-type diffused layer 2, and the information charges generated in the silicon substrate 1 are stored in the potential barrier. If the information charges that exceed an allowable amount of storage are generated in the silicon substrate 1, excess charges cross the potential barrier and are drained to the middle of the silicon substrate 1.
The width of the isolation regions 3 need to be sufficient to provide electrical isolation, even if a mask deviation is generated when the diffusion regions 4 are formed. Hence, when a pixel size is reduced when the resolution of a solid state image sensor is increased, the region occupied by the isolation regions 3 increases and transfer efficiency falls. Further, when blooming suppression control is performed by the potential of the silicon substrate 1 and the transfer electrodes 6, the potential in the diffused layers 4 cannot be controlled with high accuracy because the diffused layers 4 are subject to the influence of the isolation regions 3. The influence of the isolation regions 3 remarkably affects in the reduction of the pixel size.
An object of the present invention is to provide a solid state image sensor that prevents a reduction of transfer efficiency even if pixel size is reduced.
In one aspect of the present invention a solid state image sensor is provided. The image sensor includes a semiconductor substrate. A first semiconductor region is formed in the semiconductor substrate. The first semiconductor region has a first conductivity. A second semiconductor region is formed in the first semiconductor region. The second semiconductor region has a second conductivity that is opposite to the first conductivity. A plurality of parallel isolation regions are arranged in the second semiconductor region at predetermined intervals. A plurality of transfer regions are defined in the second semiconductor region between the isolation regions. A plurality of parallel transfer electrodes are located over the second semiconductor region. The electrodes are transverse to the isolation regions. Depth of the isolation regions is less than the depth of the second semiconductor region such that the potential of the transfer regions is affected by a potential barrier formed in the first semiconductor region rather than a potential barrier formed around the isolation regions when the intervals between the isolation regions are relatively narrow.
In another aspect of the present invention, a method for manufacturing a solid state image sensor is provided. The method includes forming a first semiconductor region that has a first conductivity in a semiconductor substrate, forming a second semiconductor region that has a second conductivity, which is opposite to the first conductivity, in the first semiconductor region by diffusing first impurities that have the second conductivity in the first semiconductor region, forming a plurality of isolation regions that have the first conductivity in the second semiconductor region, wherein the isolation regions are separated by predetermined intervals by injecting parallel stripes of second impurities that have the first conductivity in the second semiconductor region, and forming a plurality of parallel transfer electrodes over the second semiconductor region, wherein the transfer electrodes are transverse to the isolation regions.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.